What’s inside

This section just provides a high level overview for curious. Our future refactoring work is likely to change the interface.

Contains general SystemC models (no-TLM) with (Semi) Accurate Timing representation. Currently we have models for:

basic_blocks

General FPGA building blocks:

  • a D Flip-Flop model in SystemC version models/basic_blocks/FDPE.hpp and Verilog models/basic_blocks/FDPE.v

  • models/basic_blocks/tristate.hpp component, mainly needed for input/output pins

clocking

Blocks for clock generation, buffering etc:

  • models/basic_blocks/clockgen.hpp, a SystemC clock generator (divider/multiplier)

memories

Memory blocks (hardware models):

  • models/memories/flash/N25QX.hpp. A quad-spi flash model. Memory is represented as a map to allow data sparsity. Content can be configured via configure_region.

  • models/memories/sdram/generic_sdram.hpp. A simple sdram model with additional backdoor interface. The backdoor allows for copy and movement of data intra-memory. Content can be preloaded via configure_region.

network

Various blocks related to GMII interfacing:

  • models/network/mock_gmii.hpp. Provides a fake GMII interface for unit-testing

  • models/network/ethbridge.hpp. A bridge for the MAC layer of the ethernet protocol

  • models/network/network_helpers.hpp. Helpers and utilities

wishbone

Models of wishbone components:

  • models/wishbone/wbram.hpp. The model of an internal FPGA memory block (BRAM).

  • models/wishbone/or1k/or1k_instruction_tracer.hpp. A SystemC component that converts raw instruction bus accesses (wishbone) back into or1k instructions.

  • models/wishbone/or1k/or1k_data_tracer.hpp. A SystemC component that traces raw (wishbone) data transactions.

tlms

Transaction Level Models (TLMs) are in general time-agnostic. Some of them support backpressure to bridge from Timing Accurate to Timing Agnostic approach.

tlm_adapters

Logic that bridges tlm to other buses and vice-versa:

  • tlms/tlm_adapters/tlm2wishbone.hpp. Block that converts TLM requests into Wishbone transactions

tlm_common

Contains common reusable blocks, like initiators and glue logic

tlm_memories

Contains memories that support the tlm protocol:

  • tlms/tlm_memories/tlm_rom.hpp: implements a read-only memory

tlm_router

Contains routing logic for tlm messages:

  • tlms/tlm_router/tlm_router.hpp: a router with configurable number of initiators and targets. Address mapping can be configured during initialization.